In recent years, devices having a trench gate; for example, an MOSFET (U-MOS) and an insulated gate bipolar transistor (IGBT), have generally been employed as switching power devices. In such power devices, an important point is that leakage current does not flow in an “OFF” state in which no electric potential is applied to the gate. Attempts have been made to develop a power device having a high electrostatic breakdown voltage (i.e., the maximum voltage at which no leakage current flows).
The present applicant previously proposed, in, for example, Patent Document 1, enhancement of electrostatic breakdown voltage by providing a super-junction structure, and providing an insulating region at an outer peripheral portion of the device. As described in Patent Documents 2 and 3, a super-junction structure includes numerous p-layer-n-layer interfaces. In the super-junction structure, neighboring pn-interfaces jointly form a continuous depletion layer, to thereby create a wide and thick continuous depletion layer, whereby electrostatic breakdown voltage is enhanced. When such a super-junction structure is provided in a drift region of a U-MOS, or in a base region of an IGBT on the side where no channel is formed, in the super-junction structure, a region having the same conduction type as a channel (inversion layer) which is formed when the gate is ON must be formed so as to be connected to the channel.
FIG. 8.A shows the configuration of a U-MOS 900 disclosed in Patent Document 1. In the U-MOS 900, n-layers 21 and p−-layers 22 are alternately juxtaposed (in a horizontal direction) on the top surface (i.e., the surface on the top side as viewed in the sheet of FIG. 8.A) of an n+-substrate 10, thereby forming a super-junction structure 20. The super-junction structure 20 includes, for example, a plurality of the plate-like or columnar n-layers 21 and p−-layers 22 provided on the top surface of the n+-substrate 10. On the top of the super-junction structure 20 are provided p-body layers 30, and trench gates, each including a gate electrode G and a gate insulating film Ig, the p-body layers 30 and the trench gates being formed alternately. Source regions; i.e., n+-layers 40, are formed so as to be in contact with the trench gates. The n+-layers 40 are located so that they are connected to the n-layers 21 of the super-junction structure 20 via n-channels (inversion layers) which are formed in the p-body layers 30 when the gates are ON. A drain electrode D is formed on the entire bottom surface of the n+-substrate 10, and a source electrode S is formed on the top surfaces of the p-body layers 30 and the n+-layers 40.
The U-MOS 900 includes a plurality of unit cells which are continuously provided in a horizontal direction (i.e., in a left-right direction as viewed in the sheet of FIGS. 8.A and 8.B), one unit cell being shown in FIG. 8.A. The configuration of a unit cell at the extreme right of the U-MOS 900 will now be described with reference to FIG. 8.B. At the extreme right of the U-MOS 900, the super-junction structure 20 is terminated by a p−-layer 22e provided to the immediate right of the n-layer 21 corresponding to the n+-layer 40 formed on the right side of the right-end trench gate. An insulating region 90 having a width w (as measured in a horizontal direction) is formed so as to be in contact with the right surfaces of the p−-layer 22e and the p-body layer 30 provided thereon. On the right side of the insulating region 90, a p−-layer 25 is formed so as to extend to the end of the chip of the device. An upper end portion 90c of the insulating region 90 extends, by a predetermined width, over a left-side portion of the top surface of the p−-layer 25 so that the right end of the source electrode S does not come into contact with the p−-layer 25.
Thus, the super-junction structure 20 is formed in a so-called n-drift region of the n-channel U-MOS 900. In practice, the n-layers 21 serve as n-drift regions. In the U-MOS 900, when the gates are ON, electrons flow from the source electrode S, through the n+-layers 40 (source regions), n-channels (inversion layers) formed in the p-body layers 30, the n-layers 21 serving as n-drift regions, and the n+-substrate 10, to the drain electrode D. Meanwhile, when the gates are OFF, depletion layers are formed at the pn junction interfaces between the n-layers 21 and p−-layers 22 constituting the super-junction structure 20, and extend throughout the super-junction structure 20, whereby flow of leakage current is prevented.
Conventionally, in connection with a semiconductor device requiring a structure of high breakdown voltage (e.g., a power device), a shallow trench isolation structure, in which the device is isolated by a trench containing an insulating substance, has been proposed. In order to achieve high breakdown voltage in a semiconductor device having such a shallow trench isolation structure, a trench having large depth and width is required.
Such a semiconductor device having a trench isolation structure is disclosed in, for example, Patent Document 4. In the disclosed semiconductor device, a plurality of silicon (Si) partition walls are provided in a trench having a large width. The Si partition walls are expanded through thermal oxidation treatment. Thus, the trench can contain silicon oxide (SiO2); i.e., the large-width trench can contain an insulating substance.
For example, Patent Document 5 discloses a semiconductor device in which a trench contains an insulating material through spin coating. Specifically, in this semiconductor device, a trench having a large width contains an insulating substance by charging a liquid insulating material into the trench, followed by solidification of the insulating material.
[Patent Document 1] Japanese Patent Application Laid-Open (kokai) No. 2001-244461
[Patent Document 2] Japanese Patent Application Laid-Open (kokai) No. H11-233759
[Patent Document 3] Japanese Patent Application Laid-Open (kokai) No. H09-266311
[Patent Document 4] Japanese Patent Application Laid-Open (kokai) No. 2004-335568
[Patent Document 5] Japanese Patent Application Laid-Open (kokai) No. 2001-267411